Design and VLSI Implementation of Second Order Sigma-Delta Modulation ADC for I-UWB Receiver

Analog to Digital converters plays an essential role in modern mixed signal circuit design. Mixed-signal System-on-chip devices such as Analog-to-Digital Converters (ADC) have become increasingly prevalent in the semiconductor industry. Nyquist Samplers require a complicated analog low pass filter to limit the maximum frequency input to the A/D and Sample and Hold circuit. Sigma-Delta (ΣΔ) modulation based Analog to Digital (A/D) conversion technology is a cost effective alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on Digital Signal Processor ICs. In this paper Over Sampling concept is used to address the problem of power dissipation, noise in ADCs and investigating the possibilities of utilizing alternative methods to reduce the noise and power dissipation in ADC architectures. This is achieved by design techniques namely Over Sampling, Second order SigmaDelta architectures and Switched Capacitor based Sample & Hold circuits. A Second order Sigma-Delta Modulator is implemented using CMOS 0.13 μm technology using a ±1.8 V power supply. Over sampling ratio are 128 with clock frequency of 45 GHz which gives bandwidth of 20 GHz. The total power dissipation of the modulator is 60 μW. The area occupied by the modulator is 30 μm х 35 μm.